yosys
Yosys Open SYnthesis Suite
The Lens
By Erik Loyd, SaaS CEO and former COO/CFO of an AWS Premier Partner.
Updated Oct 2026
Yosys turns hardware code into hardware. You describe a circuit in Verilog, and Yosys synthesizes it into the logic gates and flip-flops an FPGA or a chip is actually built from. It's the synthesis step in OpenROAD's open chip flow, and paired with nextpnr it programs Lattice iCE40, ECP5 and Gowin FPGAs with no vendor tools at all. It's free under the ISC license.
The easy route is the free OSS CAD Suite, a nightly bundle with Yosys, nextpnr, the SBY formal checker and a VHDL plugin. Source builds need CMake 3.28 and GCC 13 or Clang 16. It's scriptable, so it fits CI. Releases ship monthly, and since 0.67 the free build reads a synthesizable subset of SystemVerilog through slang.
YosysHQ sells Tabby CAD Suite, a commercial Yosys build with industrial SystemVerilog, VHDL and SVA (the assertion language verification teams write). Its calculator lists €500/month (about $562) for freelancers and €800/month (about $899) as the base for companies. Solo and small Verilog teams: free. VHDL or assertion-heavy teams: Tabby.
The catch: inherited industrial code is exactly what's paid. Free VHDL only ships for Linux x64 and Apple Silicon, and Tabby licenses lock to one machine per 32 cores.
Free vs Self-Hosted vs Paid
open coreFree: Yosys itself (ISC license) with Verilog-2005 and, since 0.67 (July 2026), a synthesizable subset of SystemVerilog via the slang library. The free OSS CAD Suite bundles Yosys with nextpnr (FPGA place-and-route), SBY (formal verification), solvers, and a GHDL plugin for VHDL synthesis (Linux x64 and Apple Silicon only).
Self-hosted: Desktop and CI tool, nothing to host. Download the OSS CAD Suite nightly, use your distro's package (often older), or build from source with CMake 3.28+ and GCC 13 / Clang 16. Scripts (.ys files) make it repeatable in CI.
Paid: Tabby CAD Suite from YosysHQ GmbH (Vienna), priced in euros on a calculator that shows totals per month. Building blocks: support credit €500 (about $562), minimum one; node license €300 (about $337) per machine with up to 32 cores, doubled for a floating license. Default company quote (1 credit + 1 node): €800/month (about $899). Solo Bundle for freelancers and 1-person companies: €500/month (about $562), which covers 1 credit and 2 node licenses. Larger bundles (Entry, Dev, Team, Business) discount volume. Tabby adds a commercial Yosys build with industrial SystemVerilog, VHDL and SVA parsers, plus MCY mutation coverage. Reduced-cost or free offers for academia and the open source EDA community on request. USD at 1 EUR = 1.1234 USD (ECB, 2026-10-21).
Free for Verilog work and most hobby and startup FPGA flows. VHDL or SVA in production means Tabby CAD Suite, from €500/month (about $562) for a freelancer and €800/month (about $899) for a company's first seat.
What to do by team size
- Solo
- free; install the OSS CAD Suite
- Small team
- free if your design is Verilog or plain SystemVerilog
- Medium team
- Tabby CAD Suite from €800/month (about $899) once you have VHDL or SVA to synthesize or verify
- Large team
- Tabby bundles with floating licenses, priced per 32-core machine
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Trust Signals
License: ISC License
Commercial Tabby CAD Suite build is proprietary and sold separately.
Commercial use: ✓ Yes
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